פסיקות מערכות ובקרים. Components of a simple PC. I/O Device Types Block Devices. Typical Data Rates מהירות טיפוסית נתונים

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מנהל התקנים DMA Introduction to Systems Programming מבוא לתכנות מערכות Device Manager גישה יש ירה לז י כר ו ן פסיקות קלט פלט Input-Output

קובל מערכות - Computers Saul Coval Components of a simple PC CPU Video controller Memory Hard drive controller ב סיסי PC USB controller

512-32768 bytes block can be read/written individually typical: disks / floppy / CD Character Devices delivers / accepts a sequential stream

processor using a special piece of hardware standard for this device is the Intel 8259 interrupt controller, and has been since early PCs IRQ

assigned to devices to allow it to "interrupt", or send a signal, to the computer when it is finished processing.

1 מנהל התקנים DMA Introduction to Systems Programming מבוא לתכנות מערכות Device Manager גישה יש ירה לז י כר ו ן פסיקות קלט פלט Input-Output Devices, s, and I/O Architectures ניהול ציוד ה יקפי INTERRUPTS שא ול ק ו בל מערכ ו ת מחש ב י ם 2 ארכיטקטורה של קלט/פלט, מערכות ובקרים שאול קובל מערכות - Computers Saul Coval Components of a simple PC CPU Video controller Memory Hard drive controller ב סיסי PC USB controller Network controller Computer internals (inside the box ) מבנה מח שב Outside world Slide 3 I/O Device Types Block Devices block size of bytes block can be read/written individually typical: disks / floppy / CD Character Devices delivers / accepts a sequential stream of characters non-addressable typical: keyboard, mouse, printer, network Other: Monitor, Clock Slide 4 s Device interrupts are fed to the processor using a special piece of hardware standard for this device is the Intel 8259 interrupt controller, and has been since early PCs IRQ The IRQ is a number set in the computer for the interrupt request. assigned to devices to allow it to "interrupt", or send a signal, to the computer when it is finished processing. In older computers, you had to manually set the IRQ values for devices. Newer computers and operating systems use plug'n'play, which allows you to not need to set IRQ values. Typical Data Rates מהירות טיפוסית של מעבר נתונים Slide 5 Slide 6 1

2 Why s Are Used to Process Information one thing at a time appear to do many things at once multitasking operating system like Windows the processor two basic ways that the processor could do this: Polling: turns going to each device and asking if they have anything they need it to do. ing: let the devices request them when they need its attention software interrupts. used by various software programs in response to different events that occur as the operating system and applications run Slide 7 Polling & s how does the CPU know that a particular device is ready or requires attention? these requests are, generally, asynchronous software program must include routines to handle these requests 2 techniques are available to service external devices: Polling s לכידות ופסיקות (ס יים את עב ודת ו) א ו איך ה מעב ד י ודע שר כיב או ציו ד ה יקפי מ וכן דורש שר ות של המ עבד? הבקשות הם ב דרך כלל אס ינכר ונית (אי ן התאמת שעונים). התוכנה ח יי בת לכלו ל פרוצד ורות לטיפ ול בא ותם בקשות. ישנם 2 טכניקות למ תן שרות לאותם רכ י בים א ו צי וד: סריקה לצ ור ך לכ ידה פסיקות Slide 8 Polling & s Polling Run Program Interrogate device 1 Polling: CPU periodically polls ALL external devices & takes action if required s: external device indicates request for attention by sending a signal via a control line it stops the current CPU activity and responds to the device that requested attention must be written in the main program (by a programmer, in advance) high level language used Action? No Interrogate device 2 Action? No Interrogate device n Action? No Yes Yes Yes Device subroutine Device subroutine Device subroutine Slide 9 Slide 1 Polling If, after interrogating, attention is required from a particular device an appropriate subroutine is called & executed (it does not take long) when finished the CPU returns to the main program if the frequency of polling is high a significant overhead is incurred on a CPU If, however, the frequency of polling is low - events may be undetected - data lost due to latency etc. Slide 11 interrupt asserted interrupt 1 asserted Run Program (a) s service routine return registers from stack service routine return registers from stack Timer Emergency button interrupt a) generic b) specific Run Program (b) return return Timer response Program Emergency response programm Slide

3 special circuitry within a mp carries interrupt signals: Request Line (IRL) The external device sends a logic signal to the CPU when it requires attention The CPU completes current instruction first, before transferring control to - the Service Routine (ISR) ISR is a software routine but it is called by hardware ISR can occur anywhere in the main program s Data BUS How interrupts happen. Connections between devices and interrupt controller actually use interrupt lines on the bus rather than dedicated wires Slide 13 Slide 14 IRQ Lines and the System Bus The devices that use interrupts trigger them by signaling over lines provided on the ISA system bus. some of them are only used internally by the system, and therefore they are not given wires on the system bus. These are interrupts, 1, 2, 8 and 13, and are never available to expansion cards (remember, IRQ2 is now wired to IRQ9 on the motherboard). Priority priority level an old PC/XT, the priority of the interrupts is, 1, 2, 3, 4, 5, 6, 7. On a modern machine second set of eight interrupts is piped through the IRQ2 channel priorities become, 1, (8, 9, 1, 11, 12, 13, 14, 15), 3, 4, 5, 6, 7. IRQs 8 to 15 take the place of IRQ2. Non-Maskable s (NMI) can be used for serious conditions that demand the processor's immediate attention. s, Multiple Devices and Conflicts is not feasible for more than one device to use an interrupt at one time, The Nature of Resource Conflicts some of the ways that resource conflicts manifest themselves. System hangs or lockups, particularly while using a peripheral device. (Memory) parity errors on parity-enabled systems. Noise or other problems from sound cards. Junk being printed on your printer. The mouse pointer hanging and refusing to move, or moving in a stuttering fashion. Error messages from Windows 95, messages about the PC not operating at maximum performance, or the system dropping to "Safe Mode" or "MS-DOS Compatibility Mode". Errors and crashes of applications for no apparent reason. Slide 15 Slide 16 Resource Conflict Resolution general steps that can be followed to fix this sort of problem Determine what all the devices in the system are using for resources. Identify the conflicting devices. Change the resource settings on one or more of the devices so they are no longer conflicting processes in private virtual address spaces shared kernel code and data in shared address space data system call traps data...and upcalls (e.g., signals) The kernel sets up process execution contexts to virtualize the machine. Threads or processes enter the kernel for services. CPU and devices force entry to the kernel to handle exceptional events. Slide 17 Summary of IRQs and Their Typical Uses IRQ Bus Line? Priorit y Typical Default Use Other Common Uses no 1 System timer None 1 no 2 Keyboard controller 2 no (rerout ed) n/a 3 8/16-bit /16-bit 12 None; cascade for IRQs Replaced by IRQ 9 COM2 (second serial port) COM1 (first serial port) None Modems, very old (EGA) video cards, COM3 (third serial port), COM4 (fourth serial port) COM4 (fourth serial port), modems, sound cards, network cards, tape accelerator cards COM3 (third serial port), modems, sound cards, network cards, tape accelerator cards Slide

4 IRQ Bus Line? Priorit y Typical Default Use Other Common Uses IRQ Bus Line? Priority Typical Default Use Other Common Uses 5 8/16-bit 13 Sound card 6 8/16-bit /16-bit 15 Floppy disk controller LPT1 (first parallel port) LPT2 (second parallel port), LPT3 (third parallel port), COM3 (third serial port), COM4 (fourth serial port), modems, network cards, tape accelerator cards, hard disk controller on old PC/XT Tape accelerator cards LPT2 (second parallel port), COM3 (third serial port), COM4 (fourth serial port), modems, sound cards, network cards, tape accelerator cards 8 no 3 Real-time clock None 9 16-bit only 4 Network cards, sound cards, SCSI host adapters, PCI devices, rerouted IRQ2 devices bit only 16-bit only 16-bit only 13 no bit only 16-bit only PS/2 mouse Floating Point Unit (FPU / NPU / Math Coprocessor) Network cards, sound cards, SCSI host adapters, secondary IDE channel, quaternary IDE channel, PCI devices Network cards, sound cards, SCSI host adapters, VGA video cards, tertiary IDE channel, quaternary IDE channel, PCI devices Network cards, sound cards, SCSI host adapters, VGA video cards, tertiary IDE channel, PCI devices None 9 Primary IDE channel SCSI host adapters 1 Secondary IDE channel Network cards, SCS Slide 19 Slide 2 I/O Software Layers Layers of the I/O system Slide 21 Slide 22 Device-Independent Interface Buffering (a) Without a standard driver interface (b) With a standard driver interface Slide 23 (a) Unbuffered input (b) Buffering in user space (c) Buffering in the kernel followed by copying to user space (d) Double buffering in the kernel Slide

5 Buffering Options No buffering: lots of context switching. User space buffering (read syscall for n bytes): buffer needs to be pinned in memory Kernel buffer with copy: only kernel page needs to be pinned. What happens with characters received during copy? Best: double buffering in kernel: while kernel buffer is being copied, buffer 1 accepts new characters. Then they switch roles. Networking may involve many copies Slide 25 Slide 26 procedure The main program continues to run until the first interrupt is asserted in the interrupt request line (IRL) The interrupt hardware latches the signal and interrupts the CPU activity The execution starts when the CPU finishes its current job when the interrupt service routine (ISR) has finished the CPU returns to the main program (status - when left - preserved in the registers) Slide 27 Service Routine The interrupt must not lead to loss of data The content of certain registers is saved to memory. These are: program counter process status accumulator interrupt asserted return Preserve status Detect source Process response Restore status Return to interrupted program Slide 28 What Happens During an? Anatomy of a device request Complete Current Instruction Push Flags 1 TEMP 3 2 1: Instruction n Instruction n+1 Internal Intr NO NO NMI INTR NO TF Execute Next Instruction 1 YES YES YES IF 1 Acknowledge Read Type Code Set TEMP=TF IF= TF= Push CS and IP call ISR NMI NO YES Execute ISR pop IP and CS popf Resume ed Procedure 5 Disk CPU controller controller Operating system 3: Return handler 2: Process interrupt Left: sequence as seen by hardware Request sent to controller, then to disk Disk responds, signals disk controller which tells interrupt controller controller notifies CPU Right: interrupt handling (software point of view) Slide 29 Slide 3 5

Making a system call xffffffff User space Kernel space (OS) Return to caller Trap to kernel 3 Trap code in register 2 4 Increment SP 9 Call read 1 Push arguments

calls OS OS handles system call Control returns to library Library returns to user program handling Slide 31 Slide 32 Windows places the specified DPC Object on

6 Making a system call xffffffff User space Kernel space (OS) Return to caller Trap to kernel 3 Trap code in register 2 4 Increment SP 9 Call read 1 Push arguments 5 6 Sys call Dispatch handler 8 Library (read call) 7 User code System call: read(fd,buffer,length) Program pushes arguments, calls library Library sets up trap, calls OS OS handles system call Control returns to library Library returns to user program handling Slide 31 Slide 32 Windows places the specified DPC Object on the target processor's DPC queue. DPC priorities: low, medium, and high Slide 33 Slide 34 Command & Flow Command & Flow Slide 35 Slide

7 Command & Flow Command & Flow Slide 37 Slide 38 Command & Flow Command & Flow Slide 39 Slide 4 Command & Flow Command & Flow dead time Slide 41 Slide

8 Command & Flow Command & Flow dead time Slide 43 Slide 44 Command & Flow Command & Flow Slide 45 Slide 46 Command & Flow Command & Flow Slide 47 Slide

9 Command & Flow Command & Flow Slide 49 Slide 5 Command & Flow Command & Flow Slide 51 Slide 52 Command & Flow Command & Flow Slide 53 Slide

10 Command & Flow Command & Flow Slide 55 Slide 56 Command & Flow Command & Flow Slide 57 Slide 58 Command & Flow Command & Flow Slide 59 Slide 6 1

11 Command & Flow Command & Flow Slide 61 Slide 62 Transfer Statistics Ultra DMA data transfer 8 I/O s per command Includes 7 I/O s for storing the command Includes 1 I/O to read the status register in the interrupt Additional I/O s to setup DMA controller 1 per command Command & Flow Slide 63 Slide 64 Command & Flow Command & Flow Slide 65 Slide

12 Command & Flow Command & Flow Slide 67 Slide 68 Command & Flow Command & Flow Slide 69 Slide 7 Command & Flow Command & Flow Slide 71 Slide

13 Command & Flow Command & Flow Slide 73 Slide 74 Command & Flow Command & Flow Slide 75 Slide 76 Command & Flow Command & Flow Slide 77 Slide

14 Command & Flow Command & Flow Slide 79 Slide 8 Command & Flow Transfer Statistics Ultra DMA data transfer No I/O registers are memory mapped uses normal PCI memory reads and writes to retrieve commands 1 per group of I/O requests Commands that complete while an interrupt is processed will not generate an additional interrupt Slide 81 Slide 82 Command Chains Block Diagram CPB Next Address Register CPB PRD Pointer Next CPB Pointer PRD PRD PRD PIO Mode 8/16-Bits ATA/ATAPI Bus Mode Channel X ATA/ATAPI Bus 8/16-Bits Channel Y ATA Core CPB PRD Pointer Next CPB Pointer PRD PRD PRD 8/16-Bits 4KB FIFO 16-Bits 16-Bits 4KB FIFO FIFO ATA Sequencer PCI Sequencer CPB PRD Pointer PRD PRD PRD PCI Channel Arbiter Next CPB Pointer BIOS PCI Configuration Header Registers PCI Core CPB Lookup Table CPB Address CPB Address CPB Address... CPB Lookup Table Address Register 32/64-Bits Slide 83 Slide

15 Test Conditions System (Micron) 5Mhz P3 192MB RAM NT 4. SP6 Intel 8281 Chipset 33Mhz PCI slot on a 66Mhz bus Micron Northbridge Iometer Fileserver access pattern 1% Random, 8% Reads, 6% 4k blocks (remainder spread from 512 bytes to 64kbytes) Process Boot using motherboard controller (same drive for all tests) UDMA-1 card has for drives attached card is in the same slot using the same 4 drives I/O's per Second File Server Access Pattern Ultra-1 Queued 2 Ultra-1 Queued 3 Ultra-1 Queued 4 Ultra-1 Queued Outstanding I/O's Ultra-1 controller using drives that support queueing. The Ultra-1 controller does not using the queing capability of the drive. Slide 86 Slide 87 File Server Access Pattern File Server Access Pattern I/O's per Second Outstanding I/O's Ultra-1 controller using drives that do not support queueing Ultra-1 Non-Queued 2 Ultra-1 Non-Queued 3 Ultra-1 Non-Queued 4 Ultra-1 Non-Queued I/O's per Second controller using drive queing capability 1 Queued 2 Queued 3 Queued 4 Queued Outstanding I/O's Slide 88 Slide 89 File Server Access Pattern Interprocess communication I/O's per Second Overlay of Ultra-1 controller using drives that support queing with controller using queued capability. The Ultra-1 controller does not using the queing capability of the drive. 1 Ultra-1 Queued 2 Ultra-1 Queued 3 Ultra-1 Queued 4 Ultra-1 Queued 1 Queued 2 Queued 3 Queued 4 Queued Outstanding I/O's Processes want to exchange information with each other Many ways to do this, including Network Pipe (special file): A writes into pipe, and B reads from it A B Slide 9 Slide

פסיקות מערכות ובקרים. Why are interrupts important. The INT and IRET instructions. Saul Coval Computer Systems 1.

פסיקות מערכות ובקרים. Why are interrupts important. The INT and IRET instructions. Saul Coval Computer Systems 1. PIC - /Jan/00 מנהל התקנים DMA Introduction to Systems Programming מבוא לתכנות מערכות Device Manager גישה יש ירה לז י כר ו ן פסיקות קלט פלט Input-Output Devices, Controllers, and I/O Architectures ניהול